Tomita Lab.,
Department of Information Science,
Faculty of Engineering,
Kyoto University
Japanese/English
- 1997
"The Intelligent Cache Controller
of a Massively Parallel Computer JUMP-1",
In Proc. IWIA '97,
Intn'l Workshop on Innovative Architecture for Future
Generation High-Performance Processors and Systems.
- 1995
-
"A Proposal of Self-Cleanup Cache",
KUIS Technical Report #95-0006, March 1995
- 1994
-
"Overview of the JUMP-1,
an MPP Prototype for General-Purpose Parallel Computations",
in ISPAN'94
- 1993
-
"A Distributed Shared Memory Multiprocessor : ASURA
--- Memory and Cache Architectures ---",
Proc. of Supercomputing '93, pp.740-749, November 1993
www@lab3.kuis.kyoto-u.ac.jp