• J. Yao, S. Miwa, H. Shimada, and S. Tomita,
  "Optimal Pipeline Depth with Pipeline Stage Unification Adoption,"
  2nd International Workshop on Advanced Low Power Systems, pp. 7-13, June 2007. [PDF]
• H. Shimada, T. Shimada, T. Tabata, T. Kojima, K. Kise, Y. Nakashima, T. Kitamura,
  "Outline of OROCHI: A Multiple Instruction Set Executable SMT Processor,"
  International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, January 2007. [PDF]
• T. Yoshimura, K. Saito, H. Shimada, S. Miwa, Y. Nakashima, S. Mori, and S. Tomita,
  "Three Quads: An Interconnection Network for Interactive Simulations,"
  Asian Simulation Conference 2006, pp.362-366, October 2006.
• J. Yao, H. Shimada, S. Tomita, Y. Nakashima, S. Mori, and S. Tomita,
  "Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption,"
  1st International Workshop on Advanced Low Power Systems, pp. 39-46, July 2006. [PDF]
• H. Shimada, H. Ando, and T. Shimada,
  "A Hybrid Power Reduction Scheme Using Pipeline Stage Unification and Dynamic Voltage Scaling,"
  9th IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX), pp.201-214, April 2006. [PDF]
• Hajime Shimada, Hideki Ando, and Toshio Shimada,
  "Pipieline Stage Unification: A Low-Energy Consumption Technique for Future Mobile Processors,"
  The International Symposium on Low Power Electronics and Design 2003, pp.326-329, August 2003. [PDF]
• Hajime Shimada, Hideki Ando, and Toshio Shimada,
  "Pipeline Stage Unification for Low-Power Consumption,"
  The 5th International Symposium on Low-Power and High-Speed Chips (COOL Chips V), pp.194-200, April 2002. [PDF(slide)]

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